Parasitic capacitance between interconnect metal lines is one of the key contributors to integrated circuit signal delay. One technique to reduce parasitic capacitance is to replace conventional inter-metal dielectric materials with air (i.e., air gaps).
However, implementing air-gaps between metal lines in a multi-level interconnect design can present some notable challenges. For instance, conventional air-gap technologies require the use of “pinch off” methods to create air gaps between the metal lines. However, these pinch-off methods generally introduce unwanted materials onto the sidewalls of the metal lines, offsetting the capacitance benefit achieved by the air gaps.
Further, via misalignment (i.e., unlanded vias) on air-gap containing metal interconnects often leads to the air-gaps being exposed, allowing metal to fill in the air-gaps and short the circuit. This via misalignment issue results in a narrow process window, making air-gap technology economically unviable.
Therefore, improved techniques for forming air-gap containing metal interconnects would be desirable.